1. Field of the Invention
The present invention generally relates to the field of solid-state memories, particularly to semiconductor memories and, even more particularly, to the field of non-volatile memories. Specifically, the invention relates to non-volatile memories that are electrically programmable.
2. Description of the Related Art
Non-volatile memory devices are commonly used in several applications when the data stored in the memory device need to be preserved even when the power supply is off. Within the class of non-volatile memory devices, electrically programmable (and erasable) memory devices, such as flash memories, have become very popular in applications in which the data to be stored is not immutable (as it might be the case of, e.g., a consolidated code for a microprocessor), being instead necessary from time to time to store new data, or to update the data already stored.
Typically, the memory device includes an arrangement of memory cells, disposed for example in rows and columns, so as to form a matrix integrated on a chip of semiconductor material together with read/program circuits and control circuits for managing read/write operations on the memory device.
Before shipping, each memory device undergoes a testing phase, particularly, a so-called Electrical-Wafer Sorting (EWS) in which some invalid memory cells, i.e., containing invalid data bits not repairable, can be found and identified. The presence of at least one inoperative memory cell is sufficient to put the whole memory device out of use.
In order to increase the yield of the manufacturing process, commonly spare memory cells are provided, designed to be used in substitution of invalid memory cells. These spare memory cells are defined as redundancy (or redundant) cells and are identical to the memory cells of the matrix. In particular, the layout of the memory cell matrix favors the use of entire rows or entire columns of redundancy cells (redundancy rows or columns) in place of rows or columns in which a memory cell has been found defective. A number of redundancy rows or columns is chosen on the basis of a compromise between the capability of correcting the failures and the area required for implementing not only the redundancy but also possible additional on-chip circuit for managing the redundancy.
In the solutions known in the art, an additional memory is provided for mapping the rows or columns including identified defective memory cells. Typically, the additional memory stores in a non-volatile way memory addresses (associative memory) corresponding to the faulty rows or columns. For example, the additional memory may be an Electrically Erasable Programmable ROM (EEPROM) Content Addressable Memory (CAM) or also an Unerasable Programmable ROM (UPROM). An additional register is provided for storing redundancy addresses of the redundancy rows or columns to be used in substitution of the faulty rows or columns. Before any operation on the memory device the memory addresses are compared with the content of the additional memory and, if found therein, they are discarded and substituted with the associated redundancy addresses stored in the register.
One of the main disadvantages of such solutions is a penalization on the access time of a memory location, depending on the time required to carry out the comparison between received memory addresses and all the faulty memory addresses stored in the additional memory. Accordingly, the access time increases with the size of the memory device.
Many solutions are known in the art, in which the additional memory is integrated on the same chip of the memory device together with a circuitry adapted to manage the redundancy in order to render the access to the memory device completely transparent to the final user. For example, reference can be made to U.S. Pat. No. 6,301,152 B1, U.S. Pat. No. 6,418,051 B2, EP 1 357 559 A1 and EP 1 365 419 A1 of STMicroelectronics Srl, in which efforts are made also to improve the access time.
Such a choice is very advantageous, but every increase of the corrective capability of the redundancy provokes an increase of the required area for its control circuitry, as well as an increase of the whole device complexity.